The present invention relates to imaging apparatus, and more particularly relates to an imaging apparatus using an amplified MOS image sensor.
Solid-state imaging apparatus such as CCD image sensor or MOS image sensor are the apparatus for converting light into electrical signals and are widely used for example in digital cameras. FIG. 1A shows an example of the construction of a prior-art MOS image sensor.
The MOS image sensor of this example includes: unit pixels 11 disposed in a matrix each having a photodiode PD1 serving as a photoelectric conversion section, an amplification transistor M1 for amplifying detection signals of the photodiode PD1, a reset transistor M2 for resetting the detection signals of the photodiode PD1, a row select transistor M3 for selecting each row, and a pixel power supply VDD; a vertical scanning section 12 for driving the unit pixels 11; a vertical signal line 13 for outputting signal voltage of the unit pixel 11; a bias transistor M5 for causing a flow of constant current through the vertical signal line 13; a bias current adjusting voltage VBIAS for determining a current value of the bias transistor M5; a clamping capacitor C11 connected to the vertical signal line 13; a hold capacitor C12 for retaining change in voltage of the vertical signal line 13; a sample-and-hold transistor M12 for connecting between the clamping capacitor C11 and the hold capacitor C12; a clamping transistor M11 for clamping the clamping capacitor C11 and hold capacitor C12 to a predetermined voltage; a column select transistor M13 connected at one terminal thereof to one end of the hold capacitor C12 for reading signals from the hold capacitor 12 of each column; a horizontal signal line 15 connected to the other terminal of the column select transistor M13; an output amplifier 16; and a horizontal scanning section 14 for driving the column select transistor M13. It should be noted that the clamping capacitor C11, hold capacitor C12, clamping transistor M11, and sample-and-hold transistor M12 constitute a noise suppressing section 17 of every one column.
FIG. 1B schematically shows a drive timing chart for explaining operation of the MOS image sensor of the prior-art example having the construction as described. When row select pulse φ ROW1 of the first row outputted from the vertical scanning section 12 is driven to H-level, the row select transistors M3 of each unit pixel 11 of the first line are turned ON so that the signal voltage of the unit pixel 11 is outputted onto the vertical signal line 13. At this time, the sample-and-hold transistor M12 and clamping transistor M11 are turned ON by driving clamping control pulse φ CLP to H-level and sample-and-hold control pulse φ SH to H-level, so as to fix the clamping capacitor C11 and the sample-and-hold capacitor C12 to a reference potential VREF.
Next the clamping transistor M11 is turned OFF by driving the clamping control pulse φ CLP to L-level so as to bring the connecting line between the clamping capacitor C11 and the hold capacitor C12 to its floating state. Subsequently the reset transistor M2 is turned ON by driving reset control pulse φ RES1 of the first row to H-level to reset the detection signals of the photodiode PD1, and then the reset control pulse φ RES1 is returned to L-level again to turn OFF the reset transistor M2. At this time, a voltage change Δ Vsig before and after the resetting of photodiode PD1 occurs on the vertical signal line 13 and is accumulated at the hold capacitor C12 through the clamping capacitor C11 and sample-and-hold transistor M12.
Subsequently, the sample-and-hold control pulse φ SH is driven to L-level to turn OFF the sample-and-hold transistor M12 so that the signal component of photodiode PD1 is retained at the hold capacitor C12. Finally, the signal component retained at the hold capacitor C12 is sequentially read out to the horizontal signal line 15 by means of horizontal select pulses φ H1, φ H2 outputted from the horizontal scanning section 14 and is fetched from the output amplifier 16.
At this time, there is a problem when the obtained signals are formed into an image that a vertical stripe-like noise and/or dark shading in the horizontal direction occurs due to variance in the noise suppressing section 17 provided for each column or due to difference in load of the clock outputted from the horizontal scanning section 14.
In MOS image sensor of the prior-art construction, therefore, the technique as described below is employed to correct the vertical stripe-like noise and/or horizontal dark shading. Shown in FIGS. 2 and 3 are block diagrams for explaining the technique disclosed in Japanese Patent Application Laid-Open 2000-261730 with which the vertical stripe-like noise and horizontal dark shading are corrected.
FIG. 2 shows in a simplified manner the construction of the prior-art MOS image sensor shown in FIG. 1A, where like components as in FIG. 1A are denoted by like reference numerals. An OB region 1c with a surface covered with a light blocking film and an effective pixel region 1b to be used in actual image taking are provided within a full-pixel region 1a where a plurality of unit pixels are disposed in a matrix, and an upper side of the OB region 1c is determined as a vertical OB region 1d. 
FIG. 3 is a block diagram showing the construction of an imaging apparatus mounting the image sensor shown in FIG. 2. This imaging apparatus includes: an image sensor 10; an A/D conversion section 20 for changing signals from the image sensor 10 into digital signals; a vertical OB region adding/averaging section 30 for extracting and adding/averaging in the column direction the signals corresponding to the vertical OB region 1d of the image sensor 10 out of the signals from the A/D conversion section 20; a line memory 40 for retaining signals (correction data) from the vertical OB region adding/averaging section 30; a subtraction section 50 for subtracting correction data retained at the line memory 40 from imaging signals; and an image processing section 60 for effecting an image processing of and providing as image signals the signals from the subtraction section 50.
In this correction technique, those obtained by adding and averaging along the column direction the signals of the vertical OB region 1d when acquiring the imaging signals are retained at the line memory 40 as data for correction of the vertical stripe-like noise and horizontal dark shading. The vertical stripe-like noise and horizontal dark shading are then corrected by subtracting the correction data retained at the line memory 40 from the imaging signals at the time of normal image taking. Here the reason for adding/averaging along the column direction is to make the system less susceptible to random noise components.
Further there is another known technique as one disclosed in Japanese Patent Application Laid-Open Hei-10-313428 where correction data are acquired from an output obtained when light is shut out.